update runtime with new vm-instructions & improve example in main.rs
This commit is contained in:
parent
34e3d3a231
commit
2b7d974851
2 changed files with 199 additions and 218 deletions
165
src/main.rs
165
src/main.rs
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@ -42,24 +42,6 @@ fn main() {
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let main_scope = Scope::with_parent(&root_scope);
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let main_scope = Scope::with_parent(&root_scope);
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let typectx = main_scope.read().unwrap().typectx.clone();
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let typectx = main_scope.read().unwrap().typectx.clone();
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/* define type of the symbol
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*/
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main_scope.write().unwrap().declare_static_parse(
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"hello-string",
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"<Seq Char
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~Ascii
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~machine::Word>
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~<NullTerminatedSeq machine::Word>",
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);
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main_scope.write().unwrap().declare_static_parse(
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"pfxstr",
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"<Seq Char
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~Ascii
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~machine::Word>
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~<LengthPrefixedSeq machine::Word>",
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);
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/* link assembly-program to symbols
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/* link assembly-program to symbols
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*/
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*/
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linker.add_procedure(
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linker.add_procedure(
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@ -69,101 +51,78 @@ fn main() {
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"main",
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"main",
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"{
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"{
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let print-nullterm =
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let print-nullterm =
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λ str : <Ref <Seq Char~Ascii~machine::Word>>
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λ{} : < Seq Char~Ascii~machine::Word >
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~ <Ref <NullTerminatedArray machine::Word>>
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~ < NullTerminatedArray machine::Word >
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~ machine::Address
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↦ {
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~ machine::Word
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while(dup) { emit; }
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.
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emit;
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{
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};
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while (@ str) {
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emit (@ str);
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print-nullterm 'H' 'a' 'l' 'l' 'o' ' ' 'W' 'e' 'l' 't' '!' '\n' '\0';
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! str (i+ str 1);
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let print-uint =
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λx : ℕ ~ ℤ_2^64 ~ machine::UInt64
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↦ {
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if( x ) {
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print-nullterm {
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'\0';
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while( x ) {
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i+ '0' (i% x 10);
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! x (i/ x 10);
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}
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}
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};
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};
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let print-len =
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λ len : ℤ_2^64
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~ machine::UInt64
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~ machine::Word
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.
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λ str : <Ref <Seq Char~Ascii~machine::Word>>
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~ <Ref <Array machine::Word>>
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~ machine::Address
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~ machine::Word
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.
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{
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let end = (i+ str len);
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while (i- str end) {
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emit (@ str);
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! str (i+ str 1);
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}
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};
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let print-lenprefix =
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λ str : <Ref <Seq Char~Ascii~machine::Word>>
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~ <Ref <LenPrefixArray machine::Word>>
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~ <Ref <Struct
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<len ℤ_2^64
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~machine::UInt64
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~machine::Word>
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<data <Array machine::Word>>
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>>
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~ machine::Address
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~ machine::Word
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.
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{
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let len = (@ str);
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! str (i+ str 1);
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print-len len str;
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};
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let hello = λ.{
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print-nullterm hello-string;
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print-lenprefix pfxstr;
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let isquare = λx:ℤ. i* x x;
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let imagnitude2 = λx:ℤ.λy:ℤ. i+ (isquare x) (isquare y);
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let factorial = λn:ℤ.
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if( n ){ i* n (factorial (i- n 1)); }
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else { 1; };
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factorial 20;
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if ( i- (imagnitude2 10 20) 500 ) {
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emit '?';
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} else {
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} else {
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emit '!';
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emit '0';
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};
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};
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};
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emit '\n';
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let int-neg = λx : ℤ~machine::Int64~machine::Word ↦ i+ (bit-neg x) 1;
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emit (i+ '0' (isquare 3));
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let int-sign = λx : ℤ~machine::Int64~machine::Word ↦ bit-and (bit-shr x 63) 1;
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emit '\n';
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let int-lte = λ{
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a : ℤ~machine::Int64~machine::Word;
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b : ℤ~machine::Int64~machine::Word;
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} ↦ int-sign (i- a b);
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let int-max = λ{
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a : ℤ~machine::Int64~machine::Word;
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b : ℤ~machine::Int64~machine::Word;
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} ↦ if( int-lte b a ) { a; } else { b; };
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let vec3i-add = λ{
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{ ax:ℤ_2^64; ay:ℤ_2^64; az:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64>;
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{ bx:ℤ_2^64; by:ℤ_2^64; bz:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64>;
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} ↦ {
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i+ az bz;
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i+ ay by;
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i+ ax bx;
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};
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};
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hello;
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let print-vec3i =
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}",
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λ{ x:ℤ_2^64; y:ℤ_2^64; z:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64>
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↦ {
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print-nullterm '{' 'x' '=' '\0';
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print-uint x;
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print-nullterm ';' ' ' 'y' '=' '\0';
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print-uint y;
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print-nullterm ';' ' ' 'z' '=' '\0';
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print-uint z;
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print-nullterm '}' '\0';
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};
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let red-u8
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: <Fn <> Color ~ RGB ~ <Vec3 ℝ_0,1 ~ ℤ_256 ~ machine::UInt64>>
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= λ{} ↦ { 0; 0; 255; };
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let green-u8 = λ{} ↦ { 0; 255; 0; };
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let blue-u8 = λ{} ↦ { 255; 0; 0; };
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let yellow-u8 = λ{} ↦ { 0; 220; 220; };
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print-vec3i (vec3i-add green-u8 blue-u8);
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emit '\n';
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}"
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),
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),
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);
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);
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linker.add_static(
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"hello-string",
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"Hallo Welt!\n\0"
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.chars()
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.map(|c| (c as u8) as tisc::VM_Word)
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.collect(),
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);
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linker.add_static(
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"pfxstr",
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vec![
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3,
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'a' as tisc::VM_Word,
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'b' as tisc::VM_Word,
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'c' as tisc::VM_Word,
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'd' as tisc::VM_Word,
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],
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);
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let main_addr = linker
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let main_addr = linker
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.get_link_addr(&"main".into())
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.get_link_addr(&"main".into())
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.expect("'main' not linked");
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.expect("'main' not linked");
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248
src/runtime.rs
248
src/runtime.rs
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@ -18,13 +18,14 @@ pub fn init_runtime(linker: &mut Linker) -> Arc<RwLock<Scope>> {
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vec!["T~machine::Word", "T~machine::Word"],
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vec!["T~machine::Word", "T~machine::Word"],
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);
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);
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linker.add_procedure(
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/* drop topmost element
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"dup",
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*/
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tisc::Assembler::new()
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symbols.write().unwrap().declare_proc_parse(
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.inst(tisc::VM_Instruction::Dup)
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"drop",
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.build(),
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vec!["T"],
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vec!["T~machine::Word"],
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vec![],
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);
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);
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/* Put a single Ascii character on stdout
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/* Put a single Ascii character on stdout
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*/
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*/
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symbols.write().unwrap().declare_proc_parse(
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symbols.write().unwrap().declare_proc_parse(
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@ -33,14 +34,18 @@ pub fn init_runtime(linker: &mut Linker) -> Arc<RwLock<Scope>> {
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vec!["Char~Ascii~machine::Word"],
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vec!["Char~Ascii~machine::Word"],
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vec![],
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vec![],
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);
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);
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symbols.write().unwrap().declare_proc_parse(
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linker.add_procedure(
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"accept",
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"emit",
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vec![],
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tisc::Assembler::new()
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vec![],
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.inst(tisc::VM_Instruction::Emit)
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vec!["Char~Ascii~machine::Word"],
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.build(),
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);
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);
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linker.add_procedure("dup", tisc::Assembler::new().inst(tisc::VM_Instruction::Dup).build());
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linker.add_procedure("drop", tisc::Assembler::new().inst(tisc::VM_Instruction::Accept).build());
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linker.add_procedure("emit", tisc::Assembler::new().inst(tisc::VM_Instruction::Emit).build());
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linker.add_procedure("accept", tisc::Assembler::new().inst(tisc::VM_Instruction::Accept).build());
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/* The top two items must be native u64 integers,
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/* The top two items must be native u64 integers,
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* which are replaced by their sum.
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* which are replaced by their sum.
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* We do not know wheter a sum of two integers actually
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* We do not know wheter a sum of two integers actually
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@ -55,16 +60,43 @@ pub fn init_runtime(linker: &mut Linker) -> Arc<RwLock<Scope>> {
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],
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],
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vec!["ℤ_2^64~machine::UInt64~machine::Word"],
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vec!["ℤ_2^64~machine::UInt64~machine::Word"],
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);
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);
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symbols.write().unwrap().declare_proc_parse(
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linker.add_procedure(
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"i-",
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"i+",
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vec![],
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tisc::Assembler::new()
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vec![
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.inst(tisc::VM_Instruction::IntAdd)
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"ℤ_2^64~machine::UInt64~machine::Word",
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.build(),
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"ℤ_2^64~machine::UInt64~machine::Word",
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],
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vec!["ℤ_2^64~machine::UInt64~machine::Word"],
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);
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symbols.write().unwrap().declare_proc_parse(
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"i*",
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vec![],
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vec![
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"ℤ_2^64~machine::UInt64~machine::Word",
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"ℤ_2^64~machine::UInt64~machine::Word",
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],
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vec!["ℤ_2^64~machine::UInt64~machine::Word"],
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);
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symbols.write().unwrap().declare_proc_parse(
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"i/",
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vec![],
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vec![
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"ℤ_2^64~machine::UInt64~machine::Word",
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"ℤ_2^64~machine::UInt64~machine::Word",
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],
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vec!["ℤ_2^64~machine::UInt64~machine::Word"],
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);
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symbols.write().unwrap().declare_proc_parse(
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"i%",
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vec![],
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vec![
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"ℤ_2^64~machine::UInt64~machine::Word",
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"ℤ_2^64~machine::UInt64~machine::Word",
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],
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vec!["ℤ_2^64~machine::UInt64~machine::Word"],
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);
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);
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/* Floating-point Addition
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*/
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symbols.write().unwrap().declare_proc_parse(
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symbols.write().unwrap().declare_proc_parse(
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"f+",
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"f+",
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vec![],
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vec![],
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@ -75,35 +107,93 @@ pub fn init_runtime(linker: &mut Linker) -> Arc<RwLock<Scope>> {
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vec!["ℝ~machine::f64~machine::Word"],
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vec!["ℝ~machine::f64~machine::Word"],
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);
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);
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linker.add_procedure(
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"f+",
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tisc::Assembler::new()
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.inst(tisc::VM_Instruction::FltAdd)
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.build(),
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);
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/* Integer Subtraction
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*/
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symbols.write().unwrap().declare_proc_parse(
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symbols.write().unwrap().declare_proc_parse(
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"i-",
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"f-",
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vec![],
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vec![],
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vec![
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vec![
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"ℤ_2^64~machine::UInt64~machine::Word",
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"ℝ~machine::f64~machine::Word",
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"ℤ_2^64~machine::UInt64~machine::Word",
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"ℝ~machine::f64~machine::Word",
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],
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],
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vec!["ℤ_2^64~machine::UInt64~machine::Word"],
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vec!["ℝ~machine::f64~machine::Word"],
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);
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);
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linker.add_procedure(
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"i-",
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symbols.write().unwrap().declare_proc_parse(
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tisc::Assembler::new()
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"f*",
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.inst(tisc::VM_Instruction::Swap)
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vec![],
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.inst(tisc::VM_Instruction::BitNeg)
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vec![
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.lit(1)
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"ℝ~machine::f64~machine::Word",
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.inst(tisc::VM_Instruction::IntAdd)
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"ℝ~machine::f64~machine::Word",
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.inst(tisc::VM_Instruction::IntAdd)
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],
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.build(),
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vec!["ℝ~machine::f64~machine::Word"],
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);
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);
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symbols.write().unwrap().declare_proc_parse(
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"f/",
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vec![],
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vec![
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"ℝ~machine::f64~machine::Word",
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"ℝ~machine::f64~machine::Word",
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],
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vec!["ℝ~machine::f64~machine::Word"],
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);
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symbols.write().unwrap().declare_proc_parse(
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"f%",
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vec![],
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vec![
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"ℝ~machine::f64~machine::Word",
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"ℝ~machine::f64~machine::Word",
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],
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vec!["ℝ~machine::f64~machine::Word"],
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);
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linker.add_procedure("i+", tisc::Assembler::new().inst(tisc::VM_Instruction::IntAdd).build());
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linker.add_procedure("i-", tisc::Assembler::new().inst(tisc::VM_Instruction::IntSub).build());
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linker.add_procedure("i*", tisc::Assembler::new().inst(tisc::VM_Instruction::IntMul).build());
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linker.add_procedure("i/", tisc::Assembler::new().inst(tisc::VM_Instruction::IntDiv).build());
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linker.add_procedure("i%", tisc::Assembler::new().inst(tisc::VM_Instruction::IntRem).build());
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linker.add_procedure("f+", tisc::Assembler::new().inst(tisc::VM_Instruction::FltAdd).build());
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linker.add_procedure("f-", tisc::Assembler::new().inst(tisc::VM_Instruction::FltSub).build());
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linker.add_procedure("f*", tisc::Assembler::new().inst(tisc::VM_Instruction::FltMul).build());
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linker.add_procedure("f/", tisc::Assembler::new().inst(tisc::VM_Instruction::FltDiv).build());
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linker.add_procedure("f%", tisc::Assembler::new().inst(tisc::VM_Instruction::FltRem).build());
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symbols.write().unwrap().declare_proc_parse(
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"bit-neg",
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vec![], vec!["machine::Word", "machine::Word"], vec!["machine::Word"],
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);
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symbols.write().unwrap().declare_proc_parse(
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"bit-and",
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vec![], vec!["machine::Word", "machine::Word"], vec!["machine::Word"],
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);
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symbols.write().unwrap().declare_proc_parse(
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"bit-or",
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vec![], vec!["machine::Word", "machine::Word"], vec!["machine::Word"],
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);
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symbols.write().unwrap().declare_proc_parse(
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"bit-xor",
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vec![], vec!["machine::Word", "machine::Word"], vec!["machine::Word"],
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|
);
|
||||||
|
symbols.write().unwrap().declare_proc_parse(
|
||||||
|
"bit-shl",
|
||||||
|
vec![], vec!["machine::Word", "machine::Word"], vec!["machine::Word"],
|
||||||
|
);
|
||||||
|
symbols.write().unwrap().declare_proc_parse(
|
||||||
|
"bit-shr",
|
||||||
|
vec![], vec!["machine::Word", "machine::Word"], vec!["machine::Word"],
|
||||||
|
);
|
||||||
|
|
||||||
|
linker.add_procedure("bit-neg", tisc::Assembler::new().inst(tisc::VM_Instruction::BitNeg).build());
|
||||||
|
linker.add_procedure("bit-and", tisc::Assembler::new().inst(tisc::VM_Instruction::BitAnd).build());
|
||||||
|
linker.add_procedure("bit-or", tisc::Assembler::new().inst(tisc::VM_Instruction::BitOr).build());
|
||||||
|
linker.add_procedure("bit-xor", tisc::Assembler::new().inst(tisc::VM_Instruction::BitXor).build());
|
||||||
|
linker.add_procedure("bit-shl", tisc::Assembler::new().inst(tisc::VM_Instruction::BitShl).build());
|
||||||
|
linker.add_procedure("bit-shr", tisc::Assembler::new().inst(tisc::VM_Instruction::BitShr).build());
|
||||||
|
|
||||||
|
|
||||||
/* Fetch memory address
|
/* Fetch memory address
|
||||||
*/
|
*/
|
||||||
symbols.write().unwrap().declare_proc_parse(
|
symbols.write().unwrap().declare_proc_parse(
|
||||||
|
@ -112,13 +202,6 @@ pub fn init_runtime(linker: &mut Linker) -> Arc<RwLock<Scope>> {
|
||||||
vec!["<MutRef T~machine::Word>~machine::Address~machine::Word"],
|
vec!["<MutRef T~machine::Word>~machine::Address~machine::Word"],
|
||||||
vec!["T~machine::Word"],
|
vec!["T~machine::Word"],
|
||||||
);
|
);
|
||||||
linker.add_procedure(
|
|
||||||
"@",
|
|
||||||
tisc::Assembler::new()
|
|
||||||
.inst(tisc::VM_Instruction::Fetch)
|
|
||||||
.build(),
|
|
||||||
);
|
|
||||||
|
|
||||||
/* Store to memory
|
/* Store to memory
|
||||||
*/
|
*/
|
||||||
symbols.write().unwrap().declare_proc_parse(
|
symbols.write().unwrap().declare_proc_parse(
|
||||||
|
@ -130,72 +213,11 @@ pub fn init_runtime(linker: &mut Linker) -> Arc<RwLock<Scope>> {
|
||||||
],
|
],
|
||||||
vec![],
|
vec![],
|
||||||
);
|
);
|
||||||
linker.add_procedure(
|
|
||||||
"!",
|
|
||||||
tisc::Assembler::new()
|
|
||||||
.inst(tisc::VM_Instruction::Store)
|
|
||||||
.build(),
|
|
||||||
);
|
|
||||||
|
|
||||||
/*
|
linker.add_procedure("@", tisc::Assembler::new().inst(tisc::VM_Instruction::Fetch).build());
|
||||||
* let muli = λa.λb.{
|
linker.add_procedure("!", tisc::Assembler::new().inst(tisc::VM_Instruction::Store).build());
|
||||||
* let mut sum = 0;
|
|
||||||
* while( b != 0 ) {
|
|
||||||
* sum := (addi sum a);
|
|
||||||
* b := (subi b 1);
|
|
||||||
* }
|
|
||||||
* sum
|
|
||||||
* };
|
|
||||||
*/
|
|
||||||
symbols.write().unwrap().declare_proc_parse(
|
|
||||||
"i*",
|
|
||||||
vec![],
|
|
||||||
vec![
|
|
||||||
"ℤ_2^64~machine::UInt64~machine::Word",
|
|
||||||
"ℤ_2^64~machine::UInt64~machine::Word",
|
|
||||||
],
|
|
||||||
vec!["ℤ_2^64~machine::UInt64~machine::Word"],
|
|
||||||
);
|
|
||||||
|
|
||||||
linker.add_procedure(
|
|
||||||
"i*",
|
|
||||||
tisc::Assembler::new()
|
|
||||||
.lit(0) // [ a b ] -- [ a b sum ]
|
|
||||||
.while_loop(
|
|
||||||
// condition
|
|
||||||
tisc::Assembler::new()
|
|
||||||
// [ a b sum ] -- [ a b sum b ]
|
|
||||||
.lit(2)
|
|
||||||
.inst(tisc::VM_Instruction::Pick),
|
|
||||||
// body
|
|
||||||
tisc::Assembler::new()
|
|
||||||
// [ a b sum ] -- [ a b sum a ]
|
|
||||||
.lit(3)
|
|
||||||
.inst(tisc::VM_Instruction::Pick)
|
|
||||||
// [ a b sum a -- a b (sum+a) ]
|
|
||||||
.inst(tisc::VM_Instruction::IntAdd)
|
|
||||||
// [ a b sum -- a sum b ]
|
|
||||||
.inst(tisc::VM_Instruction::Swap)
|
|
||||||
// [ a sum b -- a sum b 1 ]
|
|
||||||
.lit(1)
|
|
||||||
// [ a sum b -- a sum (b-1) ]
|
|
||||||
.inst(tisc::VM_Instruction::Swap)
|
|
||||||
.call("i-")
|
|
||||||
// [ a sum b -- a b sum ]
|
|
||||||
.inst(tisc::VM_Instruction::Swap),
|
|
||||||
)
|
|
||||||
// [ a b sum -- a sum b ]
|
|
||||||
.lit(2)
|
|
||||||
.inst(tisc::VM_Instruction::Roll)
|
|
||||||
// [ a sum b -- a sum ]
|
|
||||||
.inst(tisc::VM_Instruction::Drop)
|
|
||||||
// [ a sum -- sum a ]
|
|
||||||
.lit(2)
|
|
||||||
.inst(tisc::VM_Instruction::Roll)
|
|
||||||
// [ sum a -- sum ]
|
|
||||||
.inst(tisc::VM_Instruction::Drop)
|
|
||||||
.build(),
|
|
||||||
);
|
|
||||||
|
|
||||||
symbols.write().unwrap().declare_static_parse(
|
symbols.write().unwrap().declare_static_parse(
|
||||||
"data-frame-ptr",
|
"data-frame-ptr",
|
||||||
|
|
Loading…
Reference in a new issue