From 312e97193aacda53bfb4b02796d49a420aee470f Mon Sep 17 00:00:00 2001
From: Michael Sippel <micha@fragmental.art>
Date: Wed, 15 May 2024 21:40:28 +0200
Subject: [PATCH] improve main example

---
 src/main.rs    | 84 ++++++++++++++++++++++++++++++++------------------
 src/runtime.rs |  2 +-
 2 files changed, 55 insertions(+), 31 deletions(-)

diff --git a/src/main.rs b/src/main.rs
index 9125613..39f3bc0 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -33,6 +33,17 @@ fn compile(
         .into_asm(&name.into())
 }
 
+
+/* TODO:
+ *   - Parse Comments
+ *   - write to address resulting from expression
+ *   - `::` -> '.' and allow ↦ only
+ *   - Parser error reporting
+ *   - Compiler error reporting
+ *   - Typecheck for LTExpr::Application
+ *   - typecheck & inference for rest
+ */
+
 fn main() {
     // create virtual machine with 4096 words of memory
     let mut vm = tisc::VM::new(0x1000);
@@ -55,39 +66,56 @@ fn main() {
                         ~ < NullTerminatedArray machine::Word >
                     ↦ {
                        while(dup) { emit; }
-                       emit;
+                       drop;
                     };
 
                 print-nullterm 'H' 'a' 'l' 'l' 'o' ' ' 'W' 'e' 'l' 't' '!' '\n' '\0';
 
-                let print-uint =
+                let fmt-uint =
                     λx : ℕ ~ ℤ_2^64 ~ machine::UInt64
                     ↦ {
                         if( x ) {
-                            print-nullterm {
-                                '\0';
-                                while( x ) {
-                                    i+ '0' (i% x 10);
-                                    ! x (i/ x 10);
-                                }
-                            };
+                            while( x ) {
+                                i+ '0' (i% x 10);
+                                ! x (i/ x 10);
+                            }
                         } else {
-                            emit '0';
+                            '0';
                         };
                     };
 
+                let print-uint = λx:ℕ ↦ print-nullterm (fmt-uint x) '\0';
+
                 let int-neg  = λx : ℤ~machine::Int64~machine::Word ↦ i+ (bit-neg x) 1;
                 let int-sign = λx : ℤ~machine::Int64~machine::Word ↦ bit-and (bit-shr x 63) 1;
 
-                let int-lte = λ{
-                    a : ℤ~machine::Int64~machine::Word;
-                    b : ℤ~machine::Int64~machine::Word;
+                let int-lt = λ{
+                    a : ℤ ~ machine::Int64;
+                    b : ℤ ~ machine::Int64;
                 } ↦ int-sign (i- a b);
 
+                let int-gt = λ{
+                    a : ℤ ~ machine::Int64;
+                    b : ℤ ~ machine::Int64;
+                } ↦ int-sign (i- b a);
+
+                let int-eq = λ{
+                    a : ℤ ~ machine::Int64;
+                    b : ℤ ~ machine::Int64; 
+                } ↦ if (i- a b) { 0; } else { 1; };
+
+                let int-lte = λa:ℤ.λb:ℤ ↦ bit-or (int-lt a b) (int-eq a b);
+                let int-gte = λa:ℤ.λb:ℤ ↦ bit-or (int-gt a b) (int-eq a b);
+
+                let int-min = λ{
+                    a : ℤ ~ machine::Int64;
+                    b : ℤ ~ machine::Int64;
+                } ↦ if( int-lt a b ) { a; } else { b; };
+
                 let int-max = λ{
-                    a : ℤ~machine::Int64~machine::Word;
-                    b : ℤ~machine::Int64~machine::Word;
-                } ↦ if( int-lte b a ) { a; } else { b; };
+                    a : ℤ ~ machine::Int64;
+                    b : ℤ ~ machine::Int64;
+                } ↦ if( int-gt a b ) { a; } else { b; };
 
                 let vec3i-add = λ{
                     { ax:ℤ_2^64; ay:ℤ_2^64; az:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64>;
@@ -98,27 +126,23 @@ fn main() {
                     i+ ax bx;
                 };
 
-                let print-vec3i =
+                let fmt-vec3i =
                     λ{ x:ℤ_2^64; y:ℤ_2^64; z:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64>
                     ↦ {
-                        print-nullterm '{' 'x' '=' '\0';
-                        print-uint x;
-                        print-nullterm ';' ' ' 'y' '=' '\0';
-                        print-uint y;
-                        print-nullterm ';' ' ' 'z' '=' '\0';
-                        print-uint z;
-                        print-nullterm '}' '\0';
+                        '}';
+                        fmt-uint z; '='; 'z'; ' '; ';';
+                        fmt-uint y; '='; 'y'; ' '; ';';
+                        fmt-uint x; '='; 'x'; '{';
                     };
 
-                let red-u8
+                let red-u8rgb
                     : <Fn <> Color ~ RGB ~ <Vec3 ℝ_0,1 ~ ℤ_256 ~ machine::UInt64>>
                     = λ{} ↦ { 0; 0; 255; };
-                let green-u8 = λ{} ↦ { 0; 255; 0; };
-                let blue-u8 = λ{} ↦ { 255; 0; 0; };
-                let yellow-u8 = λ{} ↦ { 0; 220; 220; };
+                let green-u8rgb = λ{} ↦ { 0; 255; 0; };
+                let blue-u8rgb = λ{} ↦ { 255; 0; 0; };
+                let yellow-u8rgb = λ{} ↦ { 0; 220; 220; };
 
-                print-vec3i (vec3i-add green-u8 blue-u8);
-                emit '\n';
+                print-nullterm (fmt-vec3i (vec3i-add green-u8rgb blue-u8rgb)) '\n' '\0';
             }"
         ),
     );
diff --git a/src/runtime.rs b/src/runtime.rs
index 6c7e1a3..8e68c05 100644
--- a/src/runtime.rs
+++ b/src/runtime.rs
@@ -42,7 +42,7 @@ pub fn init_runtime(linker: &mut Linker) -> Arc<RwLock<Scope>> {
     );
 
     linker.add_procedure("dup", tisc::Assembler::new().inst(tisc::VM_Instruction::Dup).build());
-    linker.add_procedure("drop", tisc::Assembler::new().inst(tisc::VM_Instruction::Accept).build());
+    linker.add_procedure("drop", tisc::Assembler::new().inst(tisc::VM_Instruction::Drop).build());
     linker.add_procedure("emit", tisc::Assembler::new().inst(tisc::VM_Instruction::Emit).build());
     linker.add_procedure("accept", tisc::Assembler::new().inst(tisc::VM_Instruction::Accept).build());