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syntaxAlchemist:dev2
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compare: syntaxAlchemist:2b7d974851f763431a70fe7b59728c94cfabddf7
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b336f2f847 ... 2b7d974851

4 changed files with 46 additions and 69 deletions
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9
src/lexer.rs
View file

@ -8,7 +8,7 @@ pub enum LTIRToken {
// DoubleQuote(String),
// TripleQuote(String),
Lambda,
MapsTo,
LambdaBody,
AssignType(String),
AssignValue,
@ -115,11 +115,11 @@ where
region.end += 1;
return Some((region, Ok(LTIRToken::Lambda)));
}
'↦' => {
'.' | '↦' => {
self.chars.next();
self.position += 1;
region.end += 1;
return Some((region, Ok(LTIRToken::MapsTo)));
return Some((region, Ok(LTIRToken::LambdaBody)));
}
'(' => {
self.chars.next();
@ -219,7 +219,7 @@ where
}
LexerState::TypeTerm(s) => {
if *c == '=' || *c == '↦' || *c == ';' {
if *c == '=' || *c == '.' || *c == '↦' || *c == ';' {
if let Some(token) = state.clone().into_token() {
return Some((region, Ok(token)));
}
@ -241,6 +241,7 @@ where
|| *c == ';'
|| *c == '='
|| *c == ':'
|| *c == '.'
|| *c == '↦'
{
// finish the current token

94
src/main.rs
View file

@ -33,17 +33,6 @@ fn compile(
.into_asm(&name.into())
}
/* TODO:
* - Parse Comments
* - write to address resulting from expression
* - `::` -> '.' and allow ↦ only
* - Parser error reporting
* - Compiler error reporting
* - Typecheck for LTExpr::Application
* - typecheck & inference for rest
*/
fn main() {
// create virtual machine with 4096 words of memory
let mut vm = tisc::VM::new(0x1000);
@ -62,87 +51,74 @@ fn main() {
"main",
"{
let print-nullterm =
λ{} : < Seq Char ~Ascii ~ machine.Word >
~ < NullTerminatedArray machine.Word >
λ{} : < Seq Char~Ascii~machine::Word >
~ < NullTerminatedArray machine::Word >
↦ {
while(dup) { emit; }
drop;
emit;
};
print-nullterm 'H' 'a' 'l' 'l' 'o' ' ' 'W' 'e' 'l' 't' '!' '\n' '\0';
let fmt-uint =
λx : ℕ ~ ℤ_2^64 ~ machine.UInt64
let print-uint =
λx : ℕ ~ ℤ_2^64 ~ machine::UInt64
↦ {
if( x ) {
print-nullterm {
'\0';
while( x ) {
i+ '0' (i% x 10);
! x (i/ x 10);
}
};
} else {
'0';
emit '0';
};
};
let print-uint = λx:ℕ ↦ print-nullterm (fmt-uint x) '\0';
let int-neg = λx : ℤ~machine::Int64~machine::Word ↦ i+ (bit-neg x) 1;
let int-sign = λx : ℤ~machine::Int64~machine::Word ↦ bit-and (bit-shr x 63) 1;
let int-neg = λx : ℤ ~ machine.Int64 ~ machine.Word ↦ i+ (bit-neg x) 1;
let int-sign = λx : ℤ ~ machine.Int64 ~ machine.Word ↦ bit-and (bit-shr x 63) 1;
let int-lt = λ{
a : ℤ ~ machine.Int64;
b : ℤ ~ machine.Int64;
let int-lte = λ{
a : ℤ~machine::Int64~machine::Word;
b : ℤ~machine::Int64~machine::Word;
} ↦ int-sign (i- a b);
let int-gt = λ{
a : ℤ ~ machine.Int64;
b : ℤ ~ machine.Int64;
} ↦ int-sign (i- b a);
let int-eq = λ{
a : ℤ ~ machine.Int64;
b : ℤ ~ machine.Int64;
} ↦ if (i- a b) { 0; } else { 1; };
let int-lte = λa:ℤ ↦ λb:ℤ ↦ bit-or (int-lt a b) (int-eq a b);
let int-gte = λa:ℤ ↦ λb:ℤ ↦ bit-or (int-gt a b) (int-eq a b);
let int-min = λ{
a : ℤ ~ machine.Int64;
b : ℤ ~ machine.Int64;
} ↦ if( int-lt a b ) { a; } else { b; };
let int-max = λ{
a : ℤ ~ machine.Int64;
b : ℤ ~ machine.Int64;
} ↦ if( int-gt a b ) { a; } else { b; };
a : ℤ~machine::Int64~machine::Word;
b : ℤ~machine::Int64~machine::Word;
} ↦ if( int-lte b a ) { a; } else { b; };
let vec3i-add = λ{
{ ax:ℤ_2^64; ay:ℤ_2^64; az:ℤ_2^64; } : <Vec3 ℤ_2^64~machine.UInt64>;
{ bx:ℤ_2^64; by:ℤ_2^64; bz:ℤ_2^64; } : <Vec3 ℤ_2^64~machine.UInt64>;
{ ax:ℤ_2^64; ay:ℤ_2^64; az:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64>;
{ bx:ℤ_2^64; by:ℤ_2^64; bz:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64>;
} ↦ {
i+ az bz;
i+ ay by;
i+ ax bx;
};
let fmt-vec3i =
λ{ x:ℤ_2^64; y:ℤ_2^64; z:ℤ_2^64; } : <Vec3 ℤ_2^64~machine.UInt64>
let print-vec3i =
λ{ x:ℤ_2^64; y:ℤ_2^64; z:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64>
↦ {
'}';
fmt-uint z; '='; 'z'; ' '; ';';
fmt-uint y; '='; 'y'; ' '; ';';
fmt-uint x; '='; 'x'; '{';
print-nullterm '{' 'x' '=' '\0';
print-uint x;
print-nullterm ';' ' ' 'y' '=' '\0';
print-uint y;
print-nullterm ';' ' ' 'z' '=' '\0';
print-uint z;
print-nullterm '}' '\0';
};
let red-u8rgb
: <Fn <> Color ~ RGB ~ <Vec3 ℝ_0,1 ~ ℤ_256 ~ machine.UInt64>>
let red-u8
: <Fn <> Color ~ RGB ~ <Vec3 ℝ_0,1 ~ ℤ_256 ~ machine::UInt64>>
= λ{} ↦ { 0; 0; 255; };
let green-u8rgb = λ{} ↦ { 0; 255; 0; };
let blue-u8rgb = λ{} ↦ { 255; 0; 0; };
let yellow-u8rgb = λ{} ↦ { 0; 220; 220; };
let green-u8 = λ{} ↦ { 0; 255; 0; };
let blue-u8 = λ{} ↦ { 255; 0; 0; };
let yellow-u8 = λ{} ↦ { 0; 220; 220; };
print-nullterm (fmt-vec3i (vec3i-add green-u8rgb blue-u8rgb)) '\n' '\0';
print-vec3i (vec3i-add green-u8 blue-u8);
emit '\n';
}"
),
);

2
src/parser.rs
View file

@ -309,7 +309,7 @@ where
tokens.next();
let mut variable_bindings = parse_binding_expr(typectx, tokens)?;
let _ = parse_expect(tokens, LTIRToken::MapsTo);
let _ = parse_expect(tokens, LTIRToken::LambdaBody);
let body = parse_expr(typectx, tokens)?;
return Ok(LTExpr::Abstraction {

2
src/runtime.rs
View file

@ -42,7 +42,7 @@ pub fn init_runtime(linker: &mut Linker) -> Arc<RwLock<Scope>> {
);
linker.add_procedure("dup", tisc::Assembler::new().inst(tisc::VM_Instruction::Dup).build());
linker.add_procedure("drop", tisc::Assembler::new().inst(tisc::VM_Instruction::Drop).build());
linker.add_procedure("drop", tisc::Assembler::new().inst(tisc::VM_Instruction::Accept).build());
linker.add_procedure("emit", tisc::Assembler::new().inst(tisc::VM_Instruction::Emit).build());
linker.add_procedure("accept", tisc::Assembler::new().inst(tisc::VM_Instruction::Accept).build());