syntaxAlchemist/lt-core
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improve main example

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This commit is contained in:
Michael Sippel 2024-05-15 21:40:28 +02:00
parent 2b7d974851
commit 312e97193a
Signed by: senvas
GPG key ID: F96CF119C34B64A6
2 changed files with 55 additions and 31 deletions
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84
src/main.rs
View file

@ -33,6 +33,17 @@ fn compile(
.into_asm(&name.into()) .into_asm(&name.into())
} }
/* TODO:
* - Parse Comments
* - write to address resulting from expression
* - `::` -> '.' and allow ↦ only
* - Parser error reporting
* - Compiler error reporting
* - Typecheck for LTExpr::Application
* - typecheck & inference for rest
*/
fn main() { fn main() {
// create virtual machine with 4096 words of memory // create virtual machine with 4096 words of memory
let mut vm = tisc::VM::new(0x1000); let mut vm = tisc::VM::new(0x1000);
@ -55,39 +66,56 @@ fn main() {
~ < NullTerminatedArray machine::Word > ~ < NullTerminatedArray machine::Word >
↦ { ↦ {
while(dup) { emit; } while(dup) { emit; }
emit; drop;
}; };
print-nullterm 'H' 'a' 'l' 'l' 'o' ' ' 'W' 'e' 'l' 't' '!' '\n' '\0'; print-nullterm 'H' 'a' 'l' 'l' 'o' ' ' 'W' 'e' 'l' 't' '!' '\n' '\0';
let print-uint = let fmt-uint =
λx : ℕ ~ ℤ_2^64 ~ machine::UInt64 λx : ℕ ~ ℤ_2^64 ~ machine::UInt64
↦ { ↦ {
if( x ) { if( x ) {
print-nullterm { while( x ) {
'\0'; i+ '0' (i% x 10);
while( x ) { ! x (i/ x 10);
i+ '0' (i% x 10); }
! x (i/ x 10);
}
};
} else { } else {
emit '0'; '0';
}; };
}; };
let print-uint = λx:ℕ ↦ print-nullterm (fmt-uint x) '\0';
let int-neg = λx : ℤ~machine::Int64~machine::Word ↦ i+ (bit-neg x) 1; let int-neg = λx : ℤ~machine::Int64~machine::Word ↦ i+ (bit-neg x) 1;
let int-sign = λx : ℤ~machine::Int64~machine::Word ↦ bit-and (bit-shr x 63) 1; let int-sign = λx : ℤ~machine::Int64~machine::Word ↦ bit-and (bit-shr x 63) 1;
let int-lte = λ{ let int-lt = λ{
a : ℤ~machine::Int64~machine::Word; a : ℤ ~ machine::Int64;
b : ℤ~machine::Int64~machine::Word; b : ℤ ~ machine::Int64;
} ↦ int-sign (i- a b); } ↦ int-sign (i- a b);
let int-gt = λ{
a : ℤ ~ machine::Int64;
b : ℤ ~ machine::Int64;
} ↦ int-sign (i- b a);
let int-eq = λ{
a : ℤ ~ machine::Int64;
b : ℤ ~ machine::Int64;
} ↦ if (i- a b) { 0; } else { 1; };
let int-lte = λa:ℤ.λb:ℤ ↦ bit-or (int-lt a b) (int-eq a b);
let int-gte = λa:ℤ.λb:ℤ ↦ bit-or (int-gt a b) (int-eq a b);
let int-min = λ{
a : ℤ ~ machine::Int64;
b : ℤ ~ machine::Int64;
} ↦ if( int-lt a b ) { a; } else { b; };
let int-max = λ{ let int-max = λ{
a : ℤ~machine::Int64~machine::Word; a : ℤ ~ machine::Int64;
b : ℤ~machine::Int64~machine::Word; b : ℤ ~ machine::Int64;
} ↦ if( int-lte b a ) { a; } else { b; }; } ↦ if( int-gt a b ) { a; } else { b; };
let vec3i-add = λ{ let vec3i-add = λ{
{ ax:ℤ_2^64; ay:ℤ_2^64; az:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64>; { ax:ℤ_2^64; ay:ℤ_2^64; az:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64>;
@ -98,27 +126,23 @@ fn main() {
i+ ax bx; i+ ax bx;
}; };
let print-vec3i = let fmt-vec3i =
λ{ x:ℤ_2^64; y:ℤ_2^64; z:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64> λ{ x:ℤ_2^64; y:ℤ_2^64; z:ℤ_2^64; } : <Vec3 ℤ_2^64~machine::UInt64>
↦ { ↦ {
print-nullterm '{' 'x' '=' '\0'; '}';
print-uint x; fmt-uint z; '='; 'z'; ' '; ';';
print-nullterm ';' ' ' 'y' '=' '\0'; fmt-uint y; '='; 'y'; ' '; ';';
print-uint y; fmt-uint x; '='; 'x'; '{';
print-nullterm ';' ' ' 'z' '=' '\0';
print-uint z;
print-nullterm '}' '\0';
}; };
let red-u8 let red-u8rgb
: <Fn <> Color ~ RGB ~ <Vec3 ℝ_0,1 ~ ℤ_256 ~ machine::UInt64>> : <Fn <> Color ~ RGB ~ <Vec3 ℝ_0,1 ~ ℤ_256 ~ machine::UInt64>>
= λ{} ↦ { 0; 0; 255; }; = λ{} ↦ { 0; 0; 255; };
let green-u8 = λ{} ↦ { 0; 255; 0; }; let green-u8rgb = λ{} ↦ { 0; 255; 0; };
let blue-u8 = λ{} ↦ { 255; 0; 0; }; let blue-u8rgb = λ{} ↦ { 255; 0; 0; };
let yellow-u8 = λ{} ↦ { 0; 220; 220; }; let yellow-u8rgb = λ{} ↦ { 0; 220; 220; };
print-vec3i (vec3i-add green-u8 blue-u8); print-nullterm (fmt-vec3i (vec3i-add green-u8rgb blue-u8rgb)) '\n' '\0';
emit '\n';
}" }"
), ),
); );

2
src/runtime.rs
View file

@ -42,7 +42,7 @@ pub fn init_runtime(linker: &mut Linker) -> Arc<RwLock<Scope>> {
); );
linker.add_procedure("dup", tisc::Assembler::new().inst(tisc::VM_Instruction::Dup).build()); linker.add_procedure("dup", tisc::Assembler::new().inst(tisc::VM_Instruction::Dup).build());
linker.add_procedure("drop", tisc::Assembler::new().inst(tisc::VM_Instruction::Accept).build()); linker.add_procedure("drop", tisc::Assembler::new().inst(tisc::VM_Instruction::Drop).build());
linker.add_procedure("emit", tisc::Assembler::new().inst(tisc::VM_Instruction::Emit).build()); linker.add_procedure("emit", tisc::Assembler::new().inst(tisc::VM_Instruction::Emit).build());
linker.add_procedure("accept", tisc::Assembler::new().inst(tisc::VM_Instruction::Accept).build()); linker.add_procedure("accept", tisc::Assembler::new().inst(tisc::VM_Instruction::Accept).build());